1. Field of the Invention
The present invention relates to a sequence control circuit used in a semiconductor testing apparatus for testing integrated circuits (hereafter referred to as “ICs”) such as semiconductor memory devices.
2. Description of the Related Art
A conventional semiconductor testing apparatus, which generates test patterns supplied to ICs under test in accordance with a test program, employs a sequence control circuit for controlling the sequence of execution of pattern generating instructions.
FIG. 6 shows the structure of a conventional semiconductor testing apparatus. This semiconductor testing apparatus is comprised of a sequence control circuit 100 which controls the sequence of execution of pattern generating instructions described in a test program, an instruction memory 200 which stores the pattern generating instructions, a pattern generating circuit 300 which is capable of carrying out computations such as addition and subtraction, and a comparator 400 which determines the quality of an IC under test 500.
The sequence control circuit 100 generates a program counter signal “a” in accordance with a sequence control instruction described in the test program. The sequence control circuit 100 accesses to the instruction memory 200 by means of the program counter signal “a” as a memory address, so that the instruction memory 200 outputs a pattern generating instruction k. The pattern generating circuit 300 generates a test pattern 1 supplied to the IC under test 500 and an expectation pattern m. The IC under test 500 operates in accordance with the test pattern 1 to generate an output signal n. The comparator 400 compares the expectation pattern m sent from the pattern generating circuit 300 with the output signal n sent from the IC under test 500 to determine the quality of the IC under test 500.
FIG. 7 shows an example of a partial test program for the semiconductor testing apparatus. This test program is comprised of groups of the value of a program counter, a sequence control instruction, and a pattern generating instruction. When a sequence control instruction NOOP is executed, the pattern generating instruction that is described in the line containing this NOOP instruction is executed and the count value of the program counter is increased. On the other hand, when a sequence control instruction LOOP is executed, the program counter is updated so as to jump to the address specified by the LOOP instruction, provided that instructions that are included in the range starting from the line specified by the LOOP instruction and ending with the line containing the LOOP instruction has not been executed as many as the specified number of times. In the example shown in FIG. 7, the specified number of times is “3” and the specified line is that labeled “AA”. Further, the line specified by the label AA is identical to that containing the LOOP instruction, so that the pattern generating instruction X≈X+1 contained in this line will be executed three times.
The operation of the conventional semiconductor testing apparatus will be explained with reference to the timing chart shown in FIG. 8 for the case that the apparatus executes the test program shown in FIG. 7.
The instruction memory 200 stores an instruction X=0 at address “0”, an instruction X=X+1 at address “1”, and an instruction X=0 at address “2”. Once a test is started, the sequence control circuit 100 generates the values of “0”, “1”, “1”, “1”, and “2” sequentially as a sequence of the program counter signals “a” in accordance with sequence instructions described in the test program. The instruction memory 200 receives the program counter signals “a” sequentially to generate instructions X=0, X=X+1, X=X+1, X=X+1, and X=0 as the pattern generating instructions k. The pattern generating circuit 300 receives the pattern generating instructions k, and performs computation in accordance with the received instructions to generate the values of “0”, “1”, “2”, “3”, and “0” as the test pattern 1.
The test pattern 1 thus generated is supplied to the IC under test 500. The comparator 400 compares the expectation pattern m, which is generated in line with the test pattern 1, with the sequence of the output signals n sent from the IC under test 500 to determine the quality of the IC under test 500.
Next, the structure of a conventional sequence control circuit 100 will be explained with reference to FIG. 9. The sequence control circuit 100 is comprised of an instruction memory 21 which stores sequence control instructions, a program counter control section 11, and a register 1.
The instruction memory 21 is accessed in accordance with the program counter signal “a” sent from the register 1 to generate a sequence control instruction f. The program counter control section 11 decodes the sequence control instruction f to determine the next program counter signal g (i.e. the program counter signal used in the next clock cycle). In the following clock cycle, the register 1 outputs the next program counter signal g as the program counter signal “a”, so that the similar operations are carried out as in the preceding clock cycle. By repeatedly performing the series of operations described above, the sequence control circuit 100 generates the program counter signals “a” one after another.
Next, the operation of the conventional sequence control circuit 100 will be explained for the case that the sequence control circuit 100 executes the test program shown in FIG. 7. FIG. 10 shows the waveforms of various signals generated in the sequence control circuit 100 during the execution of the test program.
Prior to the start of a test, in the instruction memory 21, an NOOP instruction is written into address “0”, a LOOP instruction is written into address “1”, and an NOOP instruction is written into address “2”. Additionally, an initial value “0” is set in the register 1. When the test is started, address “0” of the instruction memory 21 is accessed in accordance with the program counter signal “a” containing the value “0”, thus the instruction memory 21 outputs an NOOP instruction as a sequence control instruction f.
The program counter control section 11 decodes the sequence control instruction NOOP, and increases the count value of the program counter to output the increased value “1” as the next program counter signal g. In the following clock cycle, the register 1 outputs the value “1”, so that the similar operations will be performed as in the preceding clock cycle. The sequence control circuit 100 repeats the series of operations described above to generate the values of “0”, “1”, “1”, “1”, and “2” as a sequence of the program counter signal “a”.
In the above-described conventional sequence control circuit 100, access to the instruction memory 21 and the control relating to the program counter are carried out within a single clock cycle. Therefore, the maximum speed of operation of the sequence control circuit 100 is determined by the sum of the access time of the instruction memory 21 and the time that is necessary for the operation of the program counter control section 11 and is dependant on its speed. For this reason, there is a problem in that an instruction memory 21 having a shorter access time is required for faster operation and faster devices are indispensable for constituting the program counter control section 11.